The World Of Technical Life : SMPS Modeling

SMPS (Part 1) - Some basics

About the writer: Harvey Morehouse is a contractor/consultant with many years of experience using circuit analysis programs. His primary activities are in Reliability, Safety, Testability and Circuit Analysis. He may be reached at harvey.annie@verizon.net. Simple questions for which I know the answer are free. Complex questions, especially where I am ignorant of the answers, are costly!!!

Summary: SMPS design and analysis requires an understanding of many different areas of study. This article is intended to help the reader become familiar with the several different SMPS topologies, and their general performance characteristics. The major information is contained in the referenced articles.

SMPS types:

Dependent on who does the classification, several different switching converter types may be enumerated. These may include the familiar Buck, Boost, Buck-Boost, Cuuk, forward converter and flyback converter. Also listed are full-bridge, half bridge, ferro-resonant converters, as well a power factor correction converters and perhaps even a few others!

The references provide descriptions and operational information on many of these circuits as well as the more familiar ones. It is expected that the interested person will have downloaded and read those documents and is familiar with the operation and characteristics of these converters.

Analysis problems:

Modern SMPS designs are feedback control systems. One might think at first that familiar stability analysis tools could be used; however this is not the case. The typical SPICE stability analysis centers about determination of the AC phase - gain characteristics. However, SPICE calculates an AC small signal model about the DC operating point of a network. Where is the operating point of a switching transistor varying between hard on and hard off?

SMPS designs represent an extreme analysis problem. At one level, the converter is switching at frequencies reaching into the hundreds of kilohertz, however, its performance requirements are dependent on feedback shaping circuits and load filtering with long time constants. Often much analysis time is required to reach the steady state conditions. Having reached these steady state conditions, if now the load is step changed, or other conditions occur, another long simulation interval is required.

To this is the added problem of simulation of the PWM controller chips used with most SMPS designs. This could involve thousands of transistors and devices, many of which are operating as digital devices, creating numerous state changes, causing computations to slow at each transition. Analysis can be extremely time consuming. To answer the analysis problem, as well as addressing stability of designs, a combination of three general methodologies are used.

The first is the classical 'exact' method. This model provided more exact information regarding circuit performance at start up, response to step loads and other changing load conditions, audio susceptibility, EMI, and losses at the cost of long computational times. However stability cannot be examined in this method.

A second method is to replace the transistor switch and/or the PWM controller chip with an idealized switching device. This offered many advantages; however, the problem of stability analysis remains.

The third method involves averaging the effects during a switch cycle. As an example, for any topology we can model the effects on the output while the switch is 'on' and while it is off, during a single switching cycle. Now if these effects are time averaged, and the model produced instead of a switched waveform this average effect (or a signal which produced this average effect) then an 'average' operating point could be determined and a stability analysis performed. This is in fact an 'ideal transformer' application where a DC input voltage is transformed by a variable (duty-cycle) controlled transformer.

Now this presumes that the switching frequency is considerably higher than the cut-off of the output filter and other frequency sensitive elements, which is almost always true.

Practically the first method is infrequently used as such for controller chip manufacturers seldom provide detailed SPICE models. What one does find is they will provide simplified block diagrams of their chips. Typically one models the controller chip using XSPICE devices or logical functions (to minimize the computational burden) and uses this chip model with an actual switching device or, as in the second method with an idealized switching device.

The XSPICE PWM chip model can also be modified to produce a DC level proportional to the (error signal commanded) percent modulation of the switching device, producing a controlling level to an ideal variable transformer, which passes DC and is the penultimate DC - DC converter.

Classes of models:

From the preceding two general classes of practical simulation models result. These are the switched models and the averaged models.

Switched models vary in type and complexity. Some use (nearly) ideal switches and diodes to represent SMPS switching behavior while others idealize mainly the PWM controller chip, although portions of the feedback loop may also be idealized. The object here is to maintain a switching cycle model of the converter, although depending on the model and particularly the switching element, losses may be neglected. These models are suitable for use in transient analysis. In general they all neglect something, as all models of real devices must, but they are in general suited for investigation of transient SMPS behavior at both input and output terminals.

Averaged models are best suited for investigation of SMPS stability in AC analysis, as well as audio susceptibility; however their behavior under transient loading conditions as well as load levels is often close to observed behavior.

There are a large variety of models of each class. Different models are present for forward and flyback converters, buck and boost converters. And for each type, several people have developed models that have been identified with their name, such as Ridley, Ben-Yaakov and Basso models. Although NOT identified with a particular model, Dr Vincent Bello is often accorded the title as the 'father' of the averaged mode SMPS simulation.

As compared to 'exact' model representations, these models will simulate rather rapidly and produce results that closely represent actual observed behavior, and is some cases such as AC characteristics, stability which cannot otherwise be modeled.

A listing of some of the many models is present in an announcement by Spectrum Software in their Winter 2000 newsletter. These models are described in the book by Christophe Basso in his book, SMPS Power Supply Cookbook.

No attempt will be made here to describe the models or how they were derived, however some specific SMPS topologies will be discussed in later papers.

Conversion Methodologies:

There are two general methods of producing the desired output levels. The first is forward conversion, and the second is flyback mode. Each has advantages and disadvantages.

The first method uses power transformation to achieve the desired results. During the switch 'ON' time power is delivered to the load. The second stores energy during the switch conduction interval, which will be delivered when the switch is not conducting. The referenced articles describe each method.

There is even a method that delivers energy to the load during both the switch on and off intervals, producing a smooth power draw from the source instead of the typical pulsating loading. This has the effect of minimizing conducted interference at the source.

Control Methods:

One would be remiss not to mention that there are two general classes of SMPS control, namely voltage mode and current mode. Voltage mode consists of varying the switching pulse width in response to an error voltage level. This is simple, however, the supply is not inherently protected against short circuits at the output.

Current mode control uses a combination of an error voltage level AND a measure of output current to arrive at modified control of the duty cycle. More specifically, the output current is limited in magnitude causing the output current to be limited under short circuit conditions. There are more considerations than just this, which are covered in the references.

Operational Modes:

There are two general modes of operation, continuous and discontinuous. In the continuous mode, current through the filter inductor (as in a buck or boost realization) never reaches zero, and discontinuous where the current is deliberately allowed to reach zero, or 'dry out'. Discontinuous operation causes problems in modeling, as the average model has to be adjusted to allow for the third state where the output capacitor alone supplies load current. There are however advantages to discontinuous mode operation, which are described in the literature and hopefully will be covered in subsequent parts.

Many models are suitable only for the continuous mode of operation. Amazingly, ingenious yet simple models have been developed which will accommodate either and both modes of operation.

Conclusions:

It is not a trivial exercise to design and model an SMPS, as there are many subtle considerations. As one example, one can design a system that will indeed produce the desired results, however, after the design is completed, often one must consider conducted EMI at the supply mains. The inclusion of filtering can cause an otherwise stable SMPS design to become unstable.

Another pitfall could be the effects of catastrophic unloading of the converter. If the output L-C filtering is not properly chosen, the output could rise to dangerous levels destroying attached IC devices. This can occur in a single switching cycle, before the supply can respond.

However it is NOT a hopeless or impossible task to properly model operating SMPS implementations, and there are sufficient tools to enable this to be done using B2SPICE. The problems lie in the fact that most of the models are tailored to other SPICE implementations, as are the published books and articles, seemingly advertisements for those products. Subsequent parts of this discussion will examine some existing models, and provide a means of analysis of SMPS designs with B2Spice, or for that matter, any full SPICE3 simulator

SMPS (Part 2) - Buck voltage mode averaged controller modeling

Summary: In previous articles building blocks for PWM modeling have been provided. These include the perfect transformer, the variable transformer, logical functions, and magnetic elements. In this part a model for an averaged mode buck SMPS supply will be created using some or all of the ideas of previous articles and especially of the referenced materials.

A Caveat:
All models are approximations of real circuits. Their behavior may not be representative of all combinations of controller chips, switching elements and feedback circuits. It is IMPERATIVE, nay, a NECESSITY for all SMPS model behavior to be validated by comparison with the observed performance of the real circuits being modeled.

There are many different models of PWM controllers. Some, which provide PWM pulses, are suited for transient, actual switched PS modeling. These could be largely real device models, or they could be idealized representations of the manufacturer's block diagrams of the PWM controller chip. These models can be used with real switching devices, or with idealized models of the switching devices themselves.

Some specific controller chip models may be found on the net, specifically from ON Semiconductor but also from other vendors. Some of these models have prohibitions against distribution and will not be discussed here for that reason; however an individual is free to use them.

Here and in subsequent parts we will consider only those models that do not have these restrictions. Thus, aside from the general models, the only other models that will be considered will largely be those without those restrictions, and models created from the equivalent block diagrams of specific chips.

Buck SG 1524 averaged model:

Reference 1 provides a block diagram of an SG1524/LTC 1524 Controller chip, shown here in Figure 1 following:

Figure 1
LTC version of 1524 Regulator Block Diagram

(NOTE: TI and other vendors make similar devices with other features.) For this case, we shall be creating an average model of the device, and simplifying the model to remove some complexities present. Specifically, as we wish only to get a value for the duty cycle output from the device (an average or state-space model), the 'T' flip-flop, NOR gates and output transistors are not required. Also, oscillator frequency control, set by external Rt and Ct values, should be known in any given implementation and the value of the oscillator frequency will be passed to the model.

The shutdown feature and the under-voltage shutdown (available in some versions of the chip) as well as the current limit feature will not be modeled. These can be easily added, and may be useful for the transient, switching device model. But at least for now, they will not be modeled.

From Reference 2, a simple current mode controller block diagram is as shown in Figure 2 following:

Figure 2
Simplified Current Mode controller Block Diagram

Now we are getting close to the required functions to be modeled, however, there are some additions and deletions to be considered. First, the chips include a reference voltage within the chip; however it is brought out externally so that the error amplifier reference voltage may be varied externally. Second, other chips include an under-voltage lockout to prevent controller operation until the voltage to the controller reaches a certain level. Third, some chips include a 'soft-start' function that slowly increases the output driver duty cycle at turn-on. Other functions could be included in the model are duty-cycle skipping under severe overloads, overload shutoff, controller chip supply loading and more. The choice of whether or not to include them is up to the analyst.

If the function is used and is of importance to the proper functioning of the overall circuit it should be included, however, it is possible in some cases to include this external to the model. If these functions are present in an exact model, which would probably be the best tool to use to investigate these effects. If however no exact model can be found, they may be best included in this model. It is assumed that these additional considerations are not of importance here, other than the inclusion of a fixed reference voltage source.

Note that in the model of Figure 2 it is shown as a current mode controller. The current mode control can be disabled and the model used in a voltage mode by grounding the ISEN (current sense) input. But IF current sensing IS used, the duty cycle must be limited to less than 50% for stability reasons. This means that the output voltage of the converter (unless a transformer is used) is normally limited to less than half of the input voltage in a Buck application. For this paper current mode control will NOT be included, but to do so is not very burdensome.

We are now almost ready to construct a controller model, but some additional considerations are necessary. First, if we construct an error amplifier with a 'real' device model, it can be overly complex and cause simulation times to be long. If however we use an 'ideal' opamp representation, the device will not be limited in its voltage excursions. The opamp model should represent the device 'rails'. We will use an op amp model from Reference 3 that properly does this.

Secondly, the duty cycle 'D' is usually ranged from zero to unity, representing the fraction of the period of conduction. This value will later be used with a variable transformer model, to control the average voltage presented to the output filter network. This will be automatically computed in the average model variant.

Third, it is assumed that the converter (in the average case) is operating in the Continuous Conduction Mode (CCM), in that the filter inductor current never falls to zero during normal operation. This is because in this instance the value of 'D' presented to the output inductor is an average of the inductor applied voltage effects over a single cycle with two states: namely with the switch conducting and charging the inductor, and the second while the inductor discharges while the switch is open. If there is a third state, where the inductor current falls to zero (during the non-conducting switch interval), the effects of this are not properly represented by the simplest average model.

Fourth, some controllers, the 1524 being one, (Refer to Figure 1) are designed for use in a push-pull application. The internal ramp is thus at a rate twice that of the oscillator frequency, each alternate ramp controlling a separate output. Each single output should not exceed 50%. This will not affect us in our usage of it in a single ended mode with one output transistor used to provide drive. This will be transparent to us, however it is worth noting.

Fifth, some internal storage and delay time should be represented. It is not possible in the real world to have a switch on time that is infinitely variable. Some delay and storage time, both in the controller chip and the switch (or switching transistor it represents) is of necessity present.

Sixth, some of the idealized representations we will be using switch in essentially zero time. This can cause slower simulations or even non-convergence problems. Some smoothing of the outputs should be added with R-C loads where needed to effect delays and to slow transitions. Also, if an idealized switch is used to represent the transistor, its 'ON' resistance should reflect that of the transistor, and its 'OFF' resistance should be sufficiently low (reflecting actual leakage or a resistance sufficient to ease computations while not affecting circuit performance).

Now, we can list the elements needed in our representation.

1. A properly limited opamp.
2. A comparator function which computes 'D', the switch commanded 'ON' fraction of a period.
3. Delay and storage elements
4. A duty cycle limiting function
5. The variable transformer circuit (for the averaged model)

The elements will be created one-by-one in the following:

The first element is the opamp. Reference 3, Basso's book, provides a configuration that is suitable for our needs in the averaged model, with some slight modifications for the switching model. This is shown in Figure 3 (for the average model) in the following:

Figure 3
Clamped average model opamp primitive

The opamp is shown as a parameterized subcircuit, as it may be convenient to save this as a building block for other controller chip models. The formulas are shown to facilitate its use in other models and/or as part of a larger parameterized controller model.

Resistor R1 is not really necessary; still, it is convenient to add it to the primitive as a source point for controlled source G1. Controlled source G1 transforms this differential voltage into a current with a transconductance of 1mA per volt (gain = 0.001. Resistor ROL, whose magnitude is scaled by the current transconductance, establishes the low frequency, DC gain of this amplifier and the desired open-loop DC gain. Capacitor COL, similarly scaled, is used to establish the open loop pole of the device.

The output voltage magnitude across ROL and COL is clamped by the diodes and limit voltage sources shown, to prevent the output voltage excursions from exceeding the amplifier limits.

Transconductance G1 is used to convert the input voltage difference into a small current, to prevent large clamp diode voltage drops causing output voltage excursions from VLOW and VHIGH limits.

Source E1 buffers this voltage, and provides an output resistance for the device. Note that with the idealized devices we are creating in out controller chip model, the output impedance really has no major effect, however as we might wish to use this idealized opamp with 'real' devices at some time, and the inclusion is not burdensome to a SPICE analysis it is included.
The next building block to be considered is the comparator. We will use logical operators to create this device. It will be a simple nonlinear voltage source, with a smoothing R-C filter following it. The comparator uses as inputs a ramp and the error voltage amplifier output to create a PWM pulse. In our case, we wish to arrive at the value of 'D' that represents the 'on' time of the switch, ranging from zero to 49%. The usual way to compute this value is:

D = (Vo - Vlow)/(Vhigh - Vlow)

In line with the model used in the Sandler circuit (Reference 4, Figure 4.3), the controller model is passed the following parameters:

     To = the sawtooth oscillator period (per half cycle of the sawtooth)
     Td = the delay time to the start of the output drive
     Ts = storage time of the output transistor(s)
     Vp = the sawtooth peak voltage excursion
     Vm = the sawtooth minimum voltage excursion

The actual model used in Sandler's book is by Dr. Vincent Bello. As I could not find this exact model in the literature, and it is in an Intusoft library that bears a copyright notice, we will derive our own model for the controller using the parameters passed, which will differ a bit from the Bello model.

The values of Vp and Vm represent the ramp peak and minimum voltage excursions. Vo represents the error voltage. Thus if Vo varies from Vlow to Vhigh, the duty cycle commanded is from zero to 100%. One could compensate for this in our single-ended design in two ways. One obvious way is to change the value of the error amplifier peak output clamp to present the maximum excursion half that to of the ramp peak level used in the comparator function. Another way is to multiply the value of 'D' by 0.5.

As we are using the chip in a single ended application, either solution or any other, such as limiting the error amplifier maximum positive output voltage level to half that specified would also work.

IF we wished to be most general, for a switching model with a push-pull application, we could use the values as specified, with a steering flip-flop and a ramp frequency of twice that of the oscillator. But again, as a tutorial explanation of how to model a single ended Buck SMPS supply, this would obscure the process with details unnecessary for the purpose of this paper. Only if the simplified model did not properly represent the controller chip operation in the imbedded overall model, or were improper parameters passed to the model, due to design or other errors, would this be a concern to us FOR THIS USAGE.

The comparator model is a nonlinear controlled source to compute the 'D' value. The period of the pulse starts when Vo exceeds Rref (delayed by Td). The pulse end is delayed by Ts. This can be computed as:

2D = ((To + Ts) - ((Vo - Vm)/(Vp - Vm))*To + Td))/To

The first numerator term is the pulse end time, while the second numerator term is the pulse start time. The numerator is divided by the ramp period to compute the fractional 'ON' time of the pulse. The average voltage applied to the output is thus this fraction times the input voltage.

This function is so simple, using the values from the controller specification and the error amplifier output that no separate schematic would be presented. There is a problem, however. Namely that Vo could be less than Vm, and yet 'D' would still have a non-zero value. The best way to represent this would be with logical equations, such that, were Vo<Vm, D=0 else D= ((To + …………….. (Please tell me you DID read the paper I prepared on how to implement logical functions in B2SPICE!!!!!) An easy way to do this would be to multiply the above expression by a term, 'u(u(Vo-Vm)-0.5))' in the non-linear source used to compute 'D', but this is left as an exercise for the reader.

It is assumed inherently that the filter and error amplifier time constants are much longer than the oscillator period. If so, the voltage to the output filter can be represented by a cycle-by-cycle average value. The only major problem is if there is noise present that might perturb Vo during a cycle.

Certainly in a switched mode model it is a valid concern. So much so that the comparator is often 'blanked' at the start of the comparator ramp for several microseconds to prevent switch noise from affecting the commanded duty cycle.

The last item to be modeled is that of the variable transformer. This was described in a separate paper, as shown in the schematic of Figure 4 following:

Figure 4
Variable Transformer Circuit

Some explanation regarding the variable transformer as used in SMPS average modeling might be in order here. Specifically, with a duty-cycle input of 'D' at the control terminals, this device will present to the output a voltage level which is the average of that presented to the output filter over a switching cycle. Given a switched voltage input of Vin, presented for a fraction of a cycle equal to 'D', the output inductor will see a level of Vin for 'D' fraction of a cycle, and (essentially) zero for a time period of '1-D' for the remainder of the cycle. The average voltage is thus:

Vavg = D*Vin + (1-D)*0 = D*Vin

This is precisely what the variable transformer will present at its output terminals, remembering that the basis for this model is an ideal transformer that passes all frequencies including DC equally well.

Vin is applied (in the model shown) at nodes N1 and N2, with the output at nodes N3 and N4, the transformer control 'D' being applied across resistor R1. Note that these designations will change in the overall chip model, with some slight simplifications in several of the sub-elements to eliminate elements not required.

All of the elements for our controller chip average model are now present. These are shown in Figure 5 as follows:

Figure 5
1524 Averaged SMPS model

The model of Figure 5 is now complete. Averaged models are used in an AC analysis, however, the switching, representing a sampled data control system, causes Nyquist errors at intervals of half the switching frequency in the output. Most averaged models including this one do not represent these effects. Models by Ridley, derived in his thesis, or based on his methodology and some others as well do include these effects.

If the error signal at the INV terminal N3 is less than the reference level at the error amplifier input N4, the output will be at a high level. The output terminal of the error amplifier, 'Vea', provides a connection for the external compensation components, between this point and the inverting input 'N3' of the error amplifier.

Amplifier 'B3' and resistor R4 implement the comparator function. Amplifiers 'B1' and B2' with associated components are the variable transformer. The supply level is 'V1' and the output is equal to the product of 'V1' and 'D' at 'Vd'.

A netlist for this simple implementation of an averaged, continuous conduction mode controller circuit is as follows:

Circuit1
************************
* B2 Spice
************************
* B2 Spice default format (same as Berkeley Spice 3F format)

***** main circuit
R2 6 Vea 5m
ROL 11 0
C1 11 0
Vm 10 0 DC
D1 11 12 DCLAMP
E1 6 0 1
Vp 12 0 DC
D2 10 11 DCLAMP
V3 Vref 0 DC
R4 14 0 1e6
R5 15 N2 1e-9
R6 Vin 16 1m
VAm1 17 15 0
B1 16 0 i=i(vam1)*v(14,0)
B2 17 0 v=V(14,0)
G2 0 11 N4 N3 .001
B3 14 0 V=0.5*{((T0+Ts) - ((v(Vea,0)-Vm)/(Vp-Vm))*To + Td)/To}
R3 Vea 0 1Meg

.model DCLAMP D is = 2.55e-9 rs = 0.042 n = .01 tt = 5.76e-6 cjo = 1.85e-11 vj = 0.75
+ m = 0.333 bv = 1000 ibv = 9.86e-5

.END

The only interesting thing not previously mentioned is the diode model DCLAMP. Here, the 'n' emission coefficient is set at 0.1. This combined with the very low current output of the 'G1' source will make the diodes behave in a nearly ideal manner.

Because editing of the device library to remove bad models is not possible, before adding this (possibly) erroneous or unsatisfactory model to the library it will be first tested, always a good practice. Thus additional components will be used to connect to what could eventually be subcircuit nodes and test the model.

The approximate topology of the test circuit will be essentially to that of Figure 6 following:

Figure 6
Approximate 1524 Test topology

The variable transformer, shown as 'X2 PWM', is not included as it is present within the controller model. For generality this is NOT a good idea, as the output could be configured in different ways for different topology switching supplies, however this is unimportant for this illustration.

Devices C41, L1 and source V2 are present to enable AC signal injection into the circuit while preserving the DC bias levels.

There is one problem in using our controller model with this schematic, however. Namely, that there is no explicit DC feedback from the error amplifier output to the negative terminal. Without this, our simplified controller may not regulate DC properly. DC feedback does occur implicitly when the overall loop is closed. A resistor could be added across R5 and C2 of Figure 6. A value of 10,000 times that of resistor R4 (22K) or 220Meg could be added which will not affect the DC open-loop gain of the error amplifier. To be slightly more rigorous one could estimate the leakage resistance of capacitor C2. This could be added to the controller model if desired, however here we will just add a resistor to the 'external' components.

Now, using a separate schematic 'page' to connect the added components to those of Figure 5, as shown in Figure 7 following, the first test circuit becomes:

Figure 7
Average mode test circuit #1

A netlist for the circuit is as follows:

1524avg test ckt2.ckt
************************
* B2 Spice
************************
* B2 Spice default format (same as Berkeley Spice 3F format)

***** main circuit
G1 0 11 12 8 .0001
R1 11 0 10000000
C1 11 0 3.98089E-11
V1 6 0 DC 1
D1 11 7 DCLAMP
V2 7 0 DC 3.5
V3 N2 0 DC 12
D2 6 11 D2_DCLAMP
V4 12 0 DC 5
R2 14 0 1e6
R4 12 0 resistor 1K
VAm1 16 N1 0
B1 N2 0 i=i(vam1)*v(14,0)
B2 16 0 v=v(N2,0)*V(14,0)
R5 22 0 1Meg
B3 14 0 V=0.49*((V(22,0)-1)/(3.5-1))
L1 N1 Vout 100u
C2 Vout 19 220u
R6 19 0 .05K
R7 Vout 0 1
L2 Vout 25 10H
C3 25 26 1
V5 26 0 DC 1n
R8 25 8 22k
R9 25 32 1.5K
C4 32 8 6.8n
R10 8 35 47K
C5 35 22 .01u
E1 22 0 11 0 1
R3 8 22 220Meg

.model DCLAMP D is = 2.55e-9 rs = 0.042 n = .01 tt = 5.76e-6 cjo = 1.85e-11 vj = 0.75
+ m = 0.333 bv = 1000 ibv = 9.86e-5

.model D2_DCLAMP D is = 2.55e-9 rs = 0.042 n = .01 tt = 5.76e-6 cjo = 1.85e-11 vj = 0.75
+ m = 0.333 bv = 1000 ibv = 9.86e-5

.model resistor r res = 1

.END

The above circuit has L2 set to 10Hy and C3 set to a value of 1F, as for this first test we wish to see the DC performance of the circuit as well as the open loop transfer function. Analyzing this in the DC mode we can see that the steady state DC output is 5.000 volts with a 100-ohm load. The output will rise to this value in a few milliseconds.

One can add a pulsed current source across the load to see the effects of a step load on the output, roughly. A better analysis is to add an AC voltage source to V3 to estimate the effects of audio susceptibility.

Summary:

The preceding example shows in brief how to construct a PWM average controller chip model using just a block diagram and idealized elements. This is described in more detail in the referenced documents. The model created needs more work before it can be really useful.

Unless one has an exact model of a controller chip, one must do something. A good choice is to use one of the 'generic' controller chip models. There are a fair number of them, and some of these will operate in both the continuous and discontinuous conduction mode. Some will show the effects of the Nyquist sampling of the controller in the frequency response characteristics.

The purpose of this paper was NOT to prepare a 'better' model of a controller chip, as the architecture and models will generally fall into a few types better represented by models readily available for use. The problem in using these models is in understanding the required parameters to be passed, their usefulness and their limitations, and converting them into a suitable format for B2SPICE usage. In later papers, time permitting, it is intended that some generic models will be converted and a brief explanation provided.

This will not take the place of downloading information, purchasing and reading materials and studying in the area of SMPS analysis, and one is always learning that there is more and more to learn. But hopefully it will help a willing student to get started. I do not pretend to be an expert in the area of SMPS design nor modeling, but just a willing and eager student.

This set of papers will NOT be a study of state-space modeling nor of Vorperian switch modeling, as better and smarter persons than I have done much already, although I may get brave enough to do this in the future when several of the generic models have been converted and if there seems to be some interest.

SMPS (Part 3) - Chris Basso Generic Switched Controller models

Summary: In previous article a simple illustration was provided showing how one could create an idealized controller model from a controller chip block diagram. Here we shall show how to convert an existing, generic switched controller model into a B2SPICE (or any other SPICE3 product) compatible format.

Converting an existing Generic Controller Model:

One good collection of Christophe Basso controller models (and others he converted) is found in Reference 1. We shall be looking at the model he calls PWMCM, in the pSPICE collection. The name implies it is PWM model for a current mode controller. We shall rename it to be SPWMCM, where the leading S denotes a Switched model as compared to an Averaged model. His model is:

* ---------------------------------------------------------- *
* PSpice generic models library for PWM controllers working in
* Voltage Mode (PWMVM) or Current Mode (PWMCM)
* Models developped by Christophe BASSO, Toulouse (FRANCE)
* Please report any bugs or non-convergence problems to:
* CBASSO@WANADOO.FR
* These models require PSpice version 6.2a or higher
* ---------------------------------------------------------- *
******
.SUBCKT PWMCM 1 2 3 4 5 6 PARAMS:
* OUT GND COMP FB SENSE VOSC
+REF=2.5, PERIOD=5U, DUTYMAX=0.8, RAMP=5V, VOUTHI=15V,
+ROUT=10, VHIGH=3, ISINK=15M, ISOURCE=500U,
+VLOW=100M, POLE=30, GAIN=31622, VOUTLO=100M, RATIO=0.333
*
* Generic Model for Current Mode PWM controller
* Developed by Christophe BASSO, France
* PSpice compatible format
* Last modified: October 25th 1996
*
***** Generic PWM controller parameters *******
* REF ; internal reference voltage
* PERIOD ; switching period
* DUTYMAX ; maximum duty cycle
* RAMP ; ramp amplitude for compensation
* VOUTHI ; driver output voltage high
* VOUTLO ; driver output voltage low
* ROUT ; driver output resistor
***** Internal error amplifier parameters *****
* VHIGH ; maximum output voltage
* VLOW ; minimum output voltage
* ISINK ; sink capability
* ISOURCE ; source capability
* POLE ; first pole in Hertz
* GAIN ; DC open-loop gain (default=90dB)
* RATIO ; maximum peak current at max output error level
; (CM only)
***********************************************
XERR 10 4 3 2 ERRAMP PARAMS: VHIGH={VHIGH} ISINK={ISINK} ISOURCE={ISOURCE} ; error amplifier
+ VLOW={VLOW} POLE={POLE} GAIN={GAIN}
VREF 10 2 {REF} ; reference voltage
ELIM 500 2 VALUE = { V(3)*RATIO } ; max peak current = VOH*RATIO / Rsense
XCOM 5 500 12 COMP ; limit comparator
XFFL 11 82 14 13 FFLOP ; flip-flop
RDUM 13 2 1MEG
VCLK 11 2 PULSE 0 5 0 1N 1N 10N {PERIOD} ; Clock set pulses
VRAMP 6 2 PULSE 0 {RAMP} 0 {PERIOD-2N} 1N 1N {PERIOD}
VDUT 80 2 PULSE 0 5 {PERIOD*DUTYMAX} 1N 1N {(PERIOD-PERIOD*DUTYMAX)-2N} {PERIOD}
; max. duty cycle (=delay/period) delay=period-(tr+tf+tpuls)
XOR1 11 14 81 OR2 ; Clock OR FFlopD
XOR2 80 12 82 OR2 ; IMAX OR MAXduty Reset
E_BOUT 15 2 VALUE = { IF ( V(81) > 3.5, {VOUTHI}, {VOUTLO} ) }
ROUT 15 1 {ROUT} ; output resistor
.ENDS PWMCM
******

Unfortunately, the model(s) refer to other imbedded subcircuit models. Fortunately they are shown or described in other articles, and/or in his book, Reference 2. The subcircuits we need to create for this specific model are XERR (model ERRAMP), a current limited error amplifier, XCOM (model COMP), a comparator, XFFL1 (model FFLOP), an RS flip flop, XOR2 and XOR3(model OR2), an 'OR' gate, SFFL2 (model TOGGLE), a D fflop. As these devices are used in many of his models, it is convenient to create them as separately as subcircuits which can be reused. In this manner we may just call them from a netlist or if we create a schematic, add these devices. We will convert several of these subcircuits, even though they are not required for this specific conversion.

We also need to translate a logical equation, E_BOUT 15 2 VALUE = {IF( V(81)> 3.5, {VOUTHI}, {VOUTLO})}, into a B2SPICE compatible format. The equation reads, IF V(81) > 3.5 then E_BOUT = (passed parameter) VOUTHI ELSE E_BOUT = (passed parameter) VOUTLO. As this will be implemented as a non-linear source, it is convenient to convert this first. But we shall first change the equation slightly to reflect that an 'ELSE' is not directly realizable in B2SPICE.

Our realization will implement the equation, V = {VOUTLO} + u(V(81,0)-3.5) * {VOUTHI - VOUTLO}. The output thus will be equal to VOUTLO unless V(81,0)>3.5, in which case the output will be VOUTLO + (VOUTHI - VOUTLO), or VOUTHI after adding the terms.

Because some of the more complex subcircuits will require use of simpler ones, we will start creating subcircuits of the simpler ones first. The first is a 2-input comparator we will name as COMP to conform to the Basso listings. The original netlist is:

**** 2 INPUT COMPARATOR ****
.SUBCKT COMP 1 2 3
* pins + - S
E_B1 4 0 VALUE = { IF ( V(1) > V(2), 5V, 0 ) }
RD 4 3 100
CD 3 0 10P
.ENDS COMP

The schematic for COMP is shown in Figure 1 following, together with applicable equations and a symbol for the subcircuit. At this time there is a choice to be made. Sometimes for some chips the equivalent circuit shows a flip-flop, gate or other device driving a switch transistor or other circuitry. The best realization would require that the output drive capabilities such as high output levels, drive current capability and so on be capable of being modified to reflect the actual switching mode controller capabilities. We will NOT do this. Should such a requirement be present, it can be added by using an output buffer device tailored to the need. Also, the whole purpose of simplified generic models is to create somewhat idealized representations of switching mode power supplies to enable fast simulations to be performed.

Figure 1
COMP schematic, equation and symbol

It should be trivial for a reader to add this part to the database. Although it is assumed this will be added at some time to the standard library, it is also assumed that the reader is able to do this and will do it, in order to fully go through this article, as well as to enable this and other Basso or SMPS controller circuit models to be imported into B2SPICE.

The netlist for the next device to be modeled is AND2, whose listing follows.

**** 2 INPUT AND CIRCUIT ****
.SUBCKT AND2 1 2 3
E_B1 4 0 VALUE = { IF ( (V(1)>800M) & (V(2)>800M), 5V, 0 ) }
RD 4 3 100
CD 3 0 100P
.ENDS AND2
****

The schematic, equations and symbol for the AND2 subcircuit are shown in Figure 2 following:

Figure 2
AND2 schematic, equation and symbol

The netlist for the next device to be modeled is NAND2, whose listing follows.

.SUBCKT NAND2 1 2 3
E_B1 5 0 VALUE = { IF ( (V(1)>800M) & (V(2)>800M), 0V, 5V ) }
R1 5 3 400
C1 3 0 20P IC=0
.ENDS NAND2
*****

The schematic, equations and symbol for the NAND2 subcircuit are shown in Figure 3 following:

Figure 3
NAND2 schematic, equation and symbol

The netlist for the next device to be modeled is NAND3, whose listing follows.

.SUBCKT NAND3_1 1 2 3 4
E_B1 5 0 VALUE = { IF ( (V(1)>800M) & (V(2)>800M) & (V(3)>800M), 0V, 5V ) }
R1 5 4 400
C1 4 0 20P IC=5
.ENDS NAND3_1
*****

The schematic, equations and symbol for the NAND3 subcircuit are shown in Figure 4 following:

Figure 4
NAND3 schematic, equation and symbol

The netlist for the next device to be modeled is NOR2, whose listing follows.

**** 2 INPUT NOR CIRCUIT ****
.SUBCKT NOR2 1 2 3
E_B1 4 0 VALUE = { IF ( (V(1)>800M) | (V(2)>800M), 0, 5V ) }
RD 4 3 100
CD 3 0 10P
.ENDS NOR2
****

The schematic, equations and symbol for the NOR2 subcircuit are shown in Figure 5 following:

Figure 5
NOR2 schematic, equation and symbol

The netlist for the next device to be modeled is OR2, whose listing follows.

**** 2 INPUT OR CIRCUIT ****
.SUBCKT OR2 1 2 3
E_B1 4 0 VALUE = { IF ( (V(1)>800M) | (V(2)>800M), 5V, 0 ) }
RD 4 3 100
CD 3 0 10P
.ENDS OR2

The schematic, equations and symbol for the NOR2 subcircuit are shown

Figure 6
OR2 schematic, equation and symbol

The netlist for the next device to be modeled is INV, whose listing follows.

.SUBCKT INV 1 2
E_B1 3 0 VALUE = { IF ( V(1)>800M, 0, 5V ) }
R1 3 2 100
C1 2 0 10P IC=5
.ENDS INV

The schematic, equations and symbol for the INV subcircuit are shown in Figure 7 following:

Figure 7
INV schematic, equation and symbol

The netlist for the next device to be modeled is TOGGLE, whose listing follows.

**** TOGGLE CIRCUIT ****
.SUBCKT TOGGLE 1 2 11 12 5 6
* CLK D R S QB Q
X1 7 4 2 8 NAND3_0
X2 8 3 10 9 NAND3_0
X3 1 8 10 7 NAND3_1
X4 4 9 1 10 NAND3_0
X5 4 7 6 5 NAND3_1
X6 5 10 3 6 NAND3_0
X7 11 4 INV
X8 12 3 INV
.ENDS TOGGLE

Note that in the implementation there are two different NAND3 models used. There is a version with the output capacitor initial condition set to 5V and another with the initial condition at 0V, logic 'ONE' and logic 'ZERO' respectively. Why is that?

If one were to use a single NAND3 device model, they would be identical, and would initialize and tend to go to an identical DC state under certain conditions, causing convergence difficulties. These devices exhibit NO hysteresis, and the trip point would be identical for the logical equations which form the 'guts' of the equation. Moreover, the DC output level is provided by a solid 5V, not a source which could, by source stepping, alleviate this problem in some cases. The solution Chris Basso used is to set the initial conditions differently. NOTE that IF the state could be truly indeterminate in some cases, that one would have to have two different models for each NAND3 pair of a latch implementation, and multiple combinations would have to be used to cover all of the cases. In the case of three latches, as in the TOGGLE circuit, one MIGHT have to use eight combinations to cover all of the cases.

However, good design will reset logic devices to a known state, at least once the circuit stabilizes and a DC operating point is reached. Consequently the initial conditions being different will merely aid in convergence. Another solution, which has the same effect, is to slightly alter the implementation such that the gate pairs in a latch are not identical in start-up operation by adding a small resistive loading to one gate. IF the analog circuits we used to model logic devices had input impedances, and the 'Q' output were loaded with a different number of gate inputs than the 'QB' output or other loads, this would eliminate this problem. One could also make the models unique in a given implementation, with different initial conditions.

I chose to rely on the addition of resistors, where needed, to insure that the devices are slightly different and enable easy convergence. The effect is the same, but only a single NAND3 model is required at the expense of adding extraneous resistance(s).

Figure 8
TOGGLE circuit schematic

The basic circuit consists to two latches. The first is set during the clock input TRUE interval, and at the negative transition of the clock pulse the contents of the first latch is transferred into the output latch. The test circuit (corrected)for this circuit is shown in Figure 9 following:

Figure 9
TOGGLE test circuit schematic

The netlist for the next device to be modeled is FFLOP, whose listing follows.

.SUBCKT FFLOP 6 8 2 1
* S R Q Q\
E_BQB 10 0 VALUE = { IF ( (V(8)<800M) & (V(2)>800M), 0, 5V ) }
E_BQ 20 0 VALUE = { IF ( (V(6)<800M) & (V(1)>800M), 0, 5V ) }
RD1 10 1 100
CD1 1 0 10P IC=5
RD2 20 2 100
CD2 2 0 10P IC=0
.ENDS FFLOP

The schematic, equations and symbol for FFLOP are as shown in Figure 10 following.

Figure 10
FFLOP circuit, equations and symbol

This model proved interesting to create. One would believe that the model would be quite straightforward, and indeed the latch portion is just two interconnected NAND2 devices. However, the problem comes with the inversion of a logical function, namely, using the inverse of a 'u' function in an equation. Given a function

f(v) = u(v(t))

The logical INVERSE of this function is NOT -u(v(t)). Clearly the output varies between zero and some constant value, in this case unity. Negating it creates an output that varies between zero and the negated constant value. The function

f2(v) = u(-v(t))

will not work correctly in most instances if the argument is unipolar logic expression, as the same effect occurs. What we need is a logical inverse of the signal, not the arithmetic inverse of a signal. This is the function of the B3 and B4 generators. These functions could of course be incorporated into the B1 and B2 sources, however for simplicity and as an aid to understanding, separate generators were used. It would be instructive for the reader to attempt to construct their own model for an RS flip flop.

We have created a (logical) inverter model as 'INV' which could have been used with NAND2 devices to create the RS flipflop, however it seemed more reasonable not to use a sub-subcircuits in the implementation as intuitively it seems this would add to the computation time by some amount.

NOTE: All of these logical devices in this article are actual ANALOG device implementations, and one must take care in using them with both analog and digital device implementations. One or the other 'loadings' of the devices are acceptable, as there is an implicit DAC or ADC added to the output, but the output cannot be both at the same time. Also, if DIGITAL devices are used with the logic device models created herein, one will have to adjust the digital device values under the SIMULATION/MIXED MODE menu options. IF an output drives BOTH (true) digital and analog devices, an ideal non-inverting buffer must be provided to isolate the different loadings.

At first it was intended to include the XERR ERROR AMPLIFIER MODEL as a part of this article, however it became too lengthy to do. This will be done in SMPS part 4, where we will examine some implementations using that model. However, as the BB folks have been good enough to include some of these building block models in their library, and as it does require some time to proofread and edit the article, not to mention add the devices to the library, it was concluded that many persons could build on what has already been done to create their own SMPS device models. And, while this is occurring, it seemed worthwhile to digress a bit to discuss some convergence issues in a separate article (and whatever else might seem worthwhile, time permitting).

SMPS (Part 4) - Chris Basso Generic Switched Controller models

Summary: In a previous article we showed how to convert existing, generic switched controller device models into a B2SPICE (or any other SPICE3 product)compatible format. However, one element was not created, namely the ERRAMP1 model. This will be created here.

Converting an existing erroramp model:

One good collection of Christophe Basso controller device models (and others he converted) is found in Reference 1. We shall be looking at the error amplifier model he calls ERRAMP, in the file named PWMCM, in the pSPICE collection. His model (with the pertinent part in bold italics) is:

* ---------------------------------------------------------- *
* PSpice generic models library for PWM controllers working in
* Voltage Mode (PWMVM) or Current Mode (PWMCM)
* Models developed by Christophe BASSO, Toulouse (FRANCE)
* Please report any bugs or non-convergence problems to:
* CBASSO@WANADOO.FR
* These models require PSpice version 6.2a or higher
* ---------------------------------------------------------- *
******
.SUBCKT PWMCM 1 2 3 4 5 6 PARAMS:
* OUT GND COMP FB SENSE VOSC
+REF=2.5, PERIOD=5U, DUTYMAX=0.8, RAMP=5V, VOUTHI=15V,
+ROUT=10, VHIGH=3, ISINK=15M, ISOURCE=500U,
+VLOW=100M, POLE=30, GAIN=31622, VOUTLO=100M, RATIO=0.333
*
* Generic Model for Current Mode PWM controller
* Developed by Christophe BASSO, France
* PSpice compatible format
* Last modified: October 25th 1996
*
***** Generic PWM controller parameters *******
* REF ; internal reference voltage
* PERIOD ; switching period
* DUTYMAX ; maximum duty cycle
* RAMP ; ramp amplitude for compensation
* VOUTHI ; driver output voltage high
* VOUTLO ; driver output voltage low
* ROUT ; driver output resistor
***** Internal error amplifier parameters *****
* VHIGH ; maximum output voltage
* VLOW ; minimum output voltage
* ISINK ; sink capability
* ISOURCE ; source capability
* POLE ; first pole in Hertz
* GAIN ; DC open-loop gain (default=90dB)
* RATIO ; maximum peak current at max output error level
; (CM only)
***********************************************
XERR 10 4 3 2 ERRAMP PARAMS: VHIGH={VHIGH} ISINK={ISINK} ISOURCE={ISOURCE} ; error amplifier
+ VLOW={VLOW} POLE={POLE} GAIN={GAIN}
VREF 10 2 {REF} ; reference voltage
ELIM 500 2 VALUE = { V(3)*RATIO } ; max peak current = VOH*RATIO / Rsense
XCOM 5 500 12 COMP ; limit comparator
XFFL 11 82 14 13 FFLOP ; flip-flop
RDUM 13 2 1MEG
VCLK 11 2 PULSE 0 5 0 1N 1N 10N {PERIOD} ; Clock set pulses
VRAMP 6 2 PULSE 0 {RAMP} 0 {PERIOD-2N} 1N 1N {PERIOD}
VDUT 80 2 PULSE 0 5 {PERIOD*DUTYMAX} 1N 1N {(PERIOD-PERIOD*DUTYMAX)-2N} {PERIOD}
; max. duty cycle (=delay/period) delay=period-(tr+tf+tpuls)
XOR1 11 14 81 OR2 ; Clock OR FFlopD
XOR2 80 12 82 OR2 ; IMAX OR MAXduty Reset
E_BOUT 15 2 VALUE = { IF ( V(81) > 3.5, {VOUTHI}, {VOUTLO} ) }
ROUT 15 1 {ROUT} ; output resistor
.ENDS PWMCM
******
**** ERROR AMPLIFIER MODEL ****
.SUBCKT ERRAMP 20 8 3 21 PARAMS: ISINK= 15M, ISOURCE=500U, VHIGH=2.8, VLOW=100M, POLE=30, GAIN=31622
* + - OUT GND
RIN 20 8 8MEG
CP1 11 21 {1/(6.28*(GAIN/100U)*POLE)}
E1 5 21 11 21 1
R9 5 2 5
D14 2 13 DMOD
IS 13 21 {ISINK/100} ; mA
Q1 21 13 16 QPMOD
ISRC 7 3 {ISOURCE} ; uA
D12 3 7 DMOD
D15 21 11 DCLAMP
G1 21 11 20 8 100U
V1 7 21 {VHIGH-0.6V}
V4 3 16 {VLOW-38MV}
RP1 11 21 {GAIN/100U}
.MODEL QPMOD PNP
.MODEL DCLAMP D (RS=10 BV=10 IBV=0.01)
.MODEL DMOD D (TT=1N CJO=10P)
.ENDS ERRAMP

This is similar to the clamped opamp in the previous part, but with current sink and peak current information.

One might ask why we need a clamped output opamp. Or even why we need to worry greatly about the gain? The answer is that a current mode controller is sensitive to the gain of the error amplifier. The amplifier shown here has several other features that could be useful as a general basis for modeling a switching mode controller with a transistor switch.

If the error changed abruptly, then the error amplifier might reach internal limits of current and voltage that would change the output response from an ideal, unlimited case. Now in general you are NOT going to find this information in most controller chip data sheets. If you can, it will be useful to include this information. If you are creating a averaged model, you would still wish to select the opamp gain and voltage limits, as we would then wish to create a level corresponding to a duty-cycle input to a voltage variable transformer.

His model, shown as a schematic (but with no netlist) in Christophe Basso's book, reference 2, is as follows:

Figure 1
ERRAMP model

The preceding shows the model with the required parameterized inputs and the following values for the passed parameters:

ISINK = 15 mA
ISOURCE = 500 uA
VHIGH = 2.8V
VLOW = 100Mv
POLE = 30 Hz
GAIN = 31,622

This model is fine, but I believe it can be made better. We will be making some slight modifications to it.

The B2SPICE model for this device is shown in Figure 2 following:

Figure 2
Modified Erramp model

In Figure 2, the input is applied across the NINV (non-inverting) and INV (inverting) terminals. Rp is set to equal GAIN (in ohms), and Cp is set to equal 1/(2*Pi*GAIN*POLE) - in farads. The GAIN is the open loop gain of the device. POLE is the low frequency break point of the device.

Now in Chris Basso's model he used a factor of 10-4 in the G1 device. This same value divided the value of Rp and multiplied the value of Cp. The purpose of doing this is that the voltage clamp circuit used a 'real' diode tweaked to make it more ideal. By multiplying the elements to make their impedances larger, the imperfections of the clamp diode circuits can be made of lesser importance.

However we have 'perfect' diodes that do not require this artifice. Consequently, we can make the transconductance amplifier G1 gain equal to unity as opposed to his value of 10-4.

The current provided by G1 produces a voltage across Rp and Cp equal (at low frequencies) to Vin*Rp volts, where Vin is transformed into a current. As Rp is equal in value to the open loop gain, the low frequency gain is equal to GAIN (internally before output voltage and current limiting). At the frequency (POLE) value of 30Hz in this case, the gain is 3dB down, diminishing at 20dB/decade.

The perfect diode model allows the forward and the reverse breakdown to be set to exact values, with essentially no resistance in either case. In this case, one can set the breakdown voltage to -VLOW, and the forward voltage to VHIGH to limit the output to between VHIGH and VLOW in excursions.

On Chris's model D14, V4, IS and Q4 are used to set the sink current of the amplifier, while I2 and D12 set the source current limits for the device. However, there is no reason why we cannot use two current sources paralleled by 'ideal' diodes, in series, eliminating those devices.

The current limiting is interesting. If the source B1 is providing no current, then the currents of sources Isl and Is circulate entirely in ideal diodes U3 and U4. When the current from B1 is less than ISOURCE, it flows through forward biased diode U3, and also forward biases diode U4 by that same additional amount. When the load attempts to draw more that ISOURCE, then U3 is turned off and Is provides just ISOURCE to the load through U4. When B1 is sinking current, the opposite occurs, except that the current is limited to ISINK through source Is as a limiting value.

The values of the perfect diode were set to be a reverse breakdown voltage drop of -VLOW volts and a forward drop of VHIGH volts. This represents the case where a unipolar supply is used for the amplifier. (If we were using an opamp with positive and negative supply output rails of +5 and -5 volts, we would set the forward voltage and reverse breakdown voltage drops to approximately 5V and -5V respectively.)

To fully test all of the device features, several tests are required. The first test will examine the output voltage levels, and current values. Refer to Figure 3 following:

Figure 3
Modified Erramp model test1 circuit

In the circuit of Figure 3 we are using a 10Hz, 1V signal input. The load is contrived to produce charge and discharge current values that will cause current and voltage limiting to occur. A graph of the output is shown in the following Figure 4.

Figure 4
Modified Erramp model test1 graph

Although not totally clear, during the negative input interval the capacitive load is provided 0.5ma until the time that the load capacitor reaches 2.8 volts, after which the load is provided just enough current to maintain the output at 2.8v. During the positive going input interval, the load capacitor is discharged at a rate equal to or less than 15ma until the capacitor voltage reaches 0.1V. The output level excursions are between 2.8V and 0.1V, and the circuit behaves as expected.

The second test modifies the output levels to +5 and -5V. The load diode was reversed, and RL was set at 1K . Lastly, the positive and negative current excursions were set at 15ma. To ease convergence the internal resistance of perfect diodes U3 and U4 were set at 1 milliohms. A graph of the circuit with these changes is shown in Figure 5 following:

Figure 5
Modified Erramp model test2 graph

In Figure 5 we see that the current pulses are symmetrical, and of 15ma amplitude. During the positive input interval the load current is just slightly less than 5ma (due to the internal ROUT value of 10 ohms). The output excursions are between +5 and -5 V.

The next test will be with the original default passed parameters, but with a zero offset sine wave error voltage of 1V in amplitude. The amplifier will be connected in an inverting configuration with a forced gain of two. The circuit is shown in Figure 6 following:

Figure 6
Modified Erramp model test3 circuit

A graph of this circuit is shown in Figure 7 following:

Figure 7
Modified Erramp model test3 circuit graph

Initially, this seems correct. When Vin is positive, the output clips, and when it is negative, we get a positive half sine wave output. However, on close examination, we do not get a full half-wave amplified sine wave output. The peak is -2 times that of the input, however. What is going on?

Well, we have to consider that a virtual ground is only present when the forward gain is large. And, when the output is clipping, the gain is essentially zero!! Consequently, during the time when the input voltage is positive, and some of when it negative, the input signal is fed forward through the feedback resistance to the output. Normally we would not expect the error voltage to do this, but this is always a possibility. During this time the virtual ground is not present.

It is interesting to see what happens when the product input voltage level and the forced gain input signal exceeds the maximum allowed voltage excursions. Setting the input level to a 2V sine wave, we get the graph of Figure 8:

Figure 8
Modified Erramp model test4 circuit graph

In Figure 8 the loss of gain is clearly shown during the negative signal excursions. The point is that sometimes-anomalous results can occur in a simulation, and it behooves us to understand why they occur - most often due to construction or misunderstanding of the results under unusual conditions of operation.

The circuit could take some more simulation and testing to validate the results, and this has been done, however, it is left to the interested reader to delve into this in more detail. Operational amplifiers that have unipolar supply levels are often tricky and misunderstood.

Summary:

A model of an error amplifier has been prepared, which is loosely based on the model provided by Chris Basso. Several of the operational features of this model have been examined and discussed. This model should be placed into the standard library as a parameterized subcircuit model for use in SMPS models and in other places where a more exact model is not required.

SMPS (Part 5) - LT3430 model

Summary: In this article a preliminary controller chip model was created, along with some other useful elements, which may be used to create other controller chip models. The model here is NOT complete and an error was noted which is present in the model. Nonetheless it illustrates some of the thinking and steps required in creating a controller chip model.

LT3430 Datasheet Model:

Refer to Figure 1 following, which shows the block diagram for an LT3430 current mode controller chip. This was taken from the LTC datasheet for this device. It is rather interesting in that it has some unique elements shown.

Figure 1
LT3430 datasheet block diagram

The LTC datasheet for this device is reference 1. The device has a frequency control within. For very light loads, where the minimum attainable duty cycle (due to delays and storage times) would cause cycle skipping and undesirable ripple effects, an internal provision is made wherein the frequency will be lowered. There is also a foldback current limit, which serves to limit the output currents when the output is short-circuited. Other interesting features are the shutdown which has a dual mode, the synchronization feature, and a patented anti-slope current compensation scheme which is said will allow larger output currents for certain cases where the slope compensation would otherwise limit the inductor current.
The controller is a current mode controller. For those not familiar with current mode control, the differences are interesting. The output error voltage, applied to the FB input is compared to a fixed reference. When the reference is greater than the FB input, the output transistor is nominally turned off. However, a second feedback loop is present and is shown by the current comparator, which compares the error voltage to the current through the switch transistor. What this does is to turn off the switch when the current limit is exceeded. Moreover, the error signal has another signal, a slope compensation (ramp) signal, which subtracts from the error voltage.
The net effect of this is to apply a variable current to the output inductor. The current ramp, which is subtracted from the error voltage, will modify the output duty cycle. This compensation ramp and its slope is very important to operation for duty cycles greater than 50%, as current mode controllers are unstable under those conditions.
This is better seen from the circuit in Figure 2, which is a generic current mode controller.

Figure 2
Generic current mode controller

Figure 2 is taken from reference 2, which is well worth reading and understanding.
The differences are small between that of the generic current mode controller and that of Figure 1, namely the frequency control functions, the shutdown function and the arbitrary inclusions of the slope compensation and inductor current waveforms without a source for those signals. The block diagram of Figure 1, and its datasheet unfortunately do not include much information necessary to create a chip model. As was noted, and as shown in reference 2, the error amplifier gain as well as the compensation ramp slope is very important to proper circuit operation.
However, the compensation ramp slope maximum for proper operation can be deduced. In Reference 2, 'm2', the discharge slope, is approximately equal to Vo*Rs/L. In this case, we INFER that the 'L' value is chosen from the allowable range on the data sheet as being equal to 5 x 10E-6. Rs is set at .150 ohms, and Vo is chosen as 15v (as the data sheet infers), producing m2 = 15*0.15/5e-6, or, 0.45 x 10e6 volts/sec.
From equation 4, the error amplifier gain 'A' should be greater than T*Rs*Vo/L. This equals 2.25. But, there is a voltage divider gain, which should be factored in. Using a value of 1.22/15, or 15 as a worst case, the gain should exceed 34. We will use a gain of 35 as a minimum, which of course the error amplifier easily exceeds.
From equation 3, the compensation ramp down slope 'm' should be greater than (1/2)*m2, or 2.25v in 50 us.
The following assumptions are made:

1. Only total shutdown will be modeled.
2. Over-current limiting will not be modeled.
3. Temperature effects will not be modeled.
4. A smooth switch with series resistance will represent the switching transistor.
5. For simplicity, a modified version of Figure 1 will be used.
6. 'A' will be scaled for the minimum recommended value of 'L'
7. Single frequency operation will be modeled.
8. The patented anti-slope modifications will not be modeled.

If any or all of these considerations are important, or any others for that matter, it is possible to add/modify them without too much effort, save for 3, 4, 7 and 8, which would appear to present an increasing order of difficulty. (As an example, consider the error amplifier in the block diagram of Figure 1. To model this fairly accurately would require some thought and effort, as well as some characteristics of the devices involved.)
Simplified LT3430 model:
A slightly modified circuit based on Figures 1 and 2 will be created, but first in order to do so five logical elements need to be made for the realization I have chosen to make. While these could (and will) be modeled with more primitive behavioral elements already created (see the SMPS articles in the B2SPICE resources section) they will clutter up the diagram with details and for clarity they will be created as single devices. The five elements are an (analog representation) of a Leading Edge Detector (LEdet), the second is a square wave to ramp converter (LE2R), used to create the compensation ramp signal, and the third a two input summing device (SUM2), an Operational Transconductance Amplifier or OTA (OTA2, based on the OTA1 device and article), and a Trailing Edge Detector (TED).
I chose to use a single generator to create a square wave signal, operating on that signal to produce a wave train of pulses as well as a sawtooth signal. Thus a single generator/parameter could be used to vary the switcher frequency, opening the way for possible modeling of the variable frequency operation characteristics of the device at a later time if needed.
The LEdet device circuitry is shown in Figure 3 following:

Figure 3
Leading Edge Detector Circuit

The circuit is very simple and straightforward. Internal delays in devices U1, U2 and U3 cause the input signal, when triply inverted at node N3 to go false after some delay when the 'IN' signal is asserted. Thus at the leading edge of the signal applied to the 'IN' port of the device will appear at the output of the 'AND' gate. The output signal will be slightly delayed due to an RC delay incorporated into the AND gate model. This model uses a threshold of 0.8 volts (arbitrarily) as a threshold point with no hysteresis. The models were described in previous SMPS articles and will not be otherwise discussed here. A circuit for simulation of this device is shown in Figure 4 following:

Figure 4
LEdet test circuit

In this case we are applying a 200 Kc square wave to the circuit. The devices were set to provide a zero to +5V amplitude output signal. The actual amplitude in this case is not important, as the circuit will not directly drive outputs that are sensitive to this parameter. The logic elements have their own imbedded ground, as well as input and output return paths to ground. Consequently the inputs can be driven from voltage sources or from voltages referenced to ground without worrying about adding termination resistances to ground. Similarly, the outputs need not have a return path to ground.
A subcircuit was created from the netlist and added to the library with the name LEdet, under a behavioral category. The symbol for this device, after adding it to the library, is shown in the test circuit of Figure 4 driven by the same generator as the model. The purpose, of course, is to show that there were no errors made in creating the part from the subcircuit.
A graph of the output is shown in Figure 5 following:

Figure 5
LEdet test circuit graph

It is not entirely clear from Figure 5, but the outputs V(OUT) and V(OUT2) do coincide. It is important to note that the circuit MIGHT be made using models of actual devices, but this is NOT to be done in this instance. Depending on the exactness of the models chosen for the devices, this could add significant time to the simulation. Moreover, if the devices were digital devices, a digital to analog converter would have to be added to the output of the device, if only implicitly, were the output to drive analog devices. If the device were to drive both digital and analog outputs, a buffer would have to be added to one or the other of the similar outputs, as a device cannot drive both analog and digital devices at the same time.
The next needed device is one that will convert the same square wave stimulus used for the LEdet circuit/device into a sawtooth ramp, LE2R. Several methods of doing this seem possible. One would be to convert the square wave of voltage into a square wave of current, and use this to charge a capacitor. Of course this would only create a half of a sawtooth of voltage, and one would have to discharge the capacitor. Now one could invert the input voltage, and create the other half of the wave, with an appropriate discharge circuit, and sum the two signals.
Another way would be to use the LEdet output to control a current generator and a switch. The current generator will charge a capacitor through a series resistance, creating a ramp of voltage. But when the LEdet output is true, a switch will be closed, discharging the cap through a very small resistance, resetting the ramp. This seems to be much simpler to implement, and will be the scheme used.
The circuit for the LE2R is shown in Figure 6 following:

Figure 6
LE2R model

In this model B1 generator has a 1A current amplitude, and switch S1 closes momentarily when the input is true. The smooth switch used is a modified STSNOT1 device (described in another article in the Resources section of the B2Spice webpage, under the Boolean Algebraic Expressions, Number 8. Because the signal has to reset very rapidly, because of the 50 us period, the expression for the STSNOT1 device, ST1, was edited to produce a value for the current generator of:

B1 N1 N2 i = uramp(v(n3,n4)-.1)*v(n1,n2)*10000

The voltage output of the LE2R device should have an amplitude of 2.5V in 50 us. As I = C * delta V/Delta T, or, 1 = C * 2.5/50e-6, C = 20 UF.
Thus, a negative going sawtooth compensation ramp of about -1.25V amplitude with a period of 5u seconds is created.
The amplitude of the output was chosen to exceed the minimum requirements of reference 2, with an output voltage equal to 1.23V, and an inductance value 'L' of 5u henries. Rs was chosen as 0.1 ohms to agree with the values of the data sheet for the nominal current sense resistor, and to provide an amplitude which was within the internal logic level of 2.9 volts. (The voltage limited error amplifier will also be set to be within this voltage range.)
A test circuit for this device is shown in Figure 7 following:

Figure 7
LE2R test circuit

In this case the circuit shows the LE2R part created from the circuit as a test of the creation of the part creation process and to ensure that no errors were made. A simulation of this circuit is shown in Figure 8 following.

Figure 8
LE2R circuit simulation

The outputs are as expected, with v(OUTR) and v(OUTR2) outputs coinciding. The square wave source is shown for reference. Not shown is the LEdet pulse output, which occurs at the positive going transition of the v(6) source.
The next device to be created is the SUM2 function, which is very simple. This is just a nonlinear controlled source, which creates the arithmetic sum of two signals. The circuit for this device is shown in Figure 9 following:

Figure 9
SUM2 circuit

The signals to be arithmetically added are applied at the 'IN1' and 'IN2' terminals, with the arithmetic sum presented at the SUM2 output. The nonlinear dependent generator B1 has as its expression v = v(IN1) + v(IN2).
A test circuit for this device is shown in Figure 10 following.

Figure 10
SUM2 test circuit

Source V1 is a negative going ramp generator, and V2 is a sine wave generator. A graph of the simulation of this circuit is shown in Figure 11 following:

Figure 11
SUM2 test simulation graph

In Figure 11 the input negative going ramp is shown, together with the input sine wave. These are added arithmetically in the circuit, as well as in the part created for this circuit, with the outputs v(SUM2) and v(SUM22) coinciding and overlapping. The results are as anticipated.
The next device to be modeled is an Operational Transconductance Amplifier, or OTA. I had considered using a conventional error amplifier in the model, however then one would have had to sense the nature of the compensational network, or to create an uncompensated error amplifier output voltage, convert it to a current, and apply this current to the external compensational network. It is easier just to use an OTA directly.
In the OTA model we might need to include output voltage limiting as well as maximum output current limiting. OTA1 is a more primitive version of the OTA without output voltage limiting hence the OTA2 model will be used.
It should be noted that with the unipolar version of an OTA the output voltage will be limited to voltages between essentially ground and the positive supply voltage. But, the output current is bi-polar, both positive and negative in sense, while the output voltage is constrained. This means that the circuit should be capable of discharging capacitance at the output to essentially ground, and that the output current slew rate should be the same for both positive and negative going levels.
I used a 'perfect diode' implementation to limit the output voltage excursions. (The perfect diode is described in one of my articles in the B2SPICE resources WEB page.) The forward voltage was set at the output voltage maximum value, while the lower limit was set to zero. While it would have been nice to set the lower limit to a small positive value (for the output sink capability of the OTA) it was felt to be of no practical significance.
Another consideration is that the device is typically limited to voltage differences at the input terminals to magnitudes between about 0.1 to 0.3 volts for linear operation. I attempted to include such limitations in the model but it became burdensome to include. If significant performance differences are noted between my model performance, and those of the LTC model (as used in the LTC version of SPICE) then this may be added at a later date.
The model for OTA2 is shown in Figure 12 following:

Figure 12
OTA2 circuit model

The model is based on the OTA1 model. The transconductance of the B1 generator will be the product of a passed transconductance gain 'G' and the voltage difference (v(INp) - v(INm)).
ROUT and COUT represent parasitic effects in the OTA, which determine the device open loop characteristics. Figure 13 following is a test circuit for the OTA2 device. The diode PD1 is a perfect diode. Its forward voltage drop is 'vd' representing the maximum output voltage, while the reverse breakdown voltage is set to a small value. This will actually be a small negative value.

Figure 13
OTA2 test circuit

The test circuit consists of the circuitry used to create the OTA1 and OTA2 models as well as the OTA2 device that was created, so that we can compare the three outputs to insure that they are identical.
A graph of the circuit in the preceding Figure is shown in Figure 14 following:

Figure 14
OTA2 test circuit large signal graph

In Figure 14 we can see that the three outputs are identical. The lower output voltage was set at 0.1mV, and from the graph it can be seen that the output voltage is actually about -0.1 mV for each of the outputs. The upper level output is 2.6 volts, which is the setting for 'vf'. The AC characteristics of this device are of interest. Consequently, Figure 15 following shows the curve of Figure 14 expanded somewhat to show the device behavior about the zero crossing level of the input sine wave.

Figure 15
OTA2 behavior about zero

In Figure 15 the uncompensated purple trace shows the output is slightly different than that of the compensated devices shown in yellow. This is important to note. In a voltage output device, the voltage will be set and the currents will track accordingly. Here the output is a current applied to an impedance (compensating network) and this determines the voltage. Consequently the effects of the compensation network will differ from what one might intuitively expect at first glance.
With a voltage output driven device the output voltage is equal to the quotient of the output voltage and the load impedance. With a current output, the output voltage is equal to the product of the output current and the load impedance. Hence to understand the graph to follow, one must look at the complex admittance of the device to understand what is happening. Before looking at this output, try a mental exercise to try to determine what might be the result. Remember that impedance poles become admittance zeros, and impedance zeros become admittance zeros.
At any rate, Figure 16 shows an AC sweep of the outputs.

Figure 16
OTA2 output AC sweep graph

Now the plot thickens, if you will forgive the pun. The blue and orange curves are the uncompensated DB output and phase in degrees for the uncompensated OTA2 device, while the orange and yellow curves for the compensated OTA2 device.
For the both device, a low frequency gain of 52 DB is shown. This corresponds to the product of the G and delta v and ROUT producing a (2mA)*1*200K output voltage of 400, or a corresponding 52 DB voltage gain. As there is no direct path to ground in the compensating network, the low frequency gain of the compensated network is also 52 DB.
The compensated output curve shape is interesting. There are two output zeros. They cause the output gain to flatten for a bit in a mid-range after an initial drop and then finally start dropping. What this does is to control the device phase shift, and also the gain at and around the switching frequency, making the design fairly robust.
This is really getting into some stuff, which tends to be advanced, even with the voltage driven compensation networks we are all used to. Consequently as most uses of the LT3430 will be somewhat cookbook, and the data sheet provides guidelines for choosing a compensation network it will be best left unsaid at this time.
The last device to be modeled here is the TED circuit. (A NO smooth switch type 1 which was described in a separate article will also be used.) Like the LED circuit, this is based on behavioral device models already in the library. The TED circuit is shown in Figure 17 following:

Figure 17
Trailing Edge Detector (TED) circuit

The circuit is very straightforward in operation. Two pairs of inverters were shown in of the inputs to U6. The purpose is to ensure the trailing edge detector output is long enough for our purposes. A test circuit is shown in Figure 18 following:

Figure 18
TED test Circuit

In Figure 18 we can see the test circuit. U7 is the LED circuit converted into a subcircuit, whose output will be compared to the model to ensure the LED and TED outputs do not coincide and work properly.
Examination of the output(s) for the circuit of Figure 18 reveals that the leading and trailing edge outputs do behave as intended, and that the outputs are distinct. A plot of the TED output is shown in Figure 19 following:

Figure 19
TED test circuit output graph

An astute viewer will note that, whereas the LED output is within the positive pulse output, the TED output is not. This is of no essential importance here as long as the usage of the signals does not, in themselves, limit the maximum modulator pulse width output. Were that the case, one would have to perform more work by adding delays to ensure that the time from the nominal 'SET' to 'RESET' pulses was the maximum attainable pulse width time. This is not the case here.
Now, having all of the essential elements, modeling of the LT3430 can proceed. Note that the values of the devices modeled for use in the final realization have been customized for use in this controller chip. If one were to use them within other chip realizations they might need to be changed for those applications.
The model for the LT3430 is shown in Figure 20 following:

Figure 20
LM3430 model

In this model the various elements are comprised in most instances by behavioral elements that have been presented in my articles in the Resources page, or described herein. It may be seen that the topology is very similar to that of Figure 2 with the exception of the error amplifier. Other differences between this and Figure 1 is that output current sensing is referenced to zero rather than to the input high level VS, and a smooth switch model is used in place of the output transistor.
In most cases the use of a smooth switch in place of an actual device will not affect the results, other than in investigation of the behavior of an actual switching transistor. As we have no details available regarding this device, as we have no controls over its switching behavior in any event, and as details of he device are not know, there really is little else we can do without more information.
The boost function is not modeled, as it is essentially meaningless in this realization, as are the BIAS and SYNC functions.
U6 is the TED, which resets the U4 FF, as well as the ramp output. U10 prevents the controller chip from operating until the input voltage, vs, is greater than 5v. U9 also shuts down the controller chip when the command level is greater than 2.38 v.
The ideal compensation slope has been already determined. The remaining step is to insure that the error amplifier gain is proper for this configuration. As shown in reference 2, the error amplifier should have a minimum gain value at half the switching frequency (100Kc). From Figure 16 we can see the gain at this frequency is about 40dB, which would correspond to a value of about 100.
Figure 21 following is the test circuit for this implementation.

Figure 21
LM3430sm test circuit

It should be noted that in this realization that current senseVam2 is really part of the chip model, and should be imbedded within the chip model. The reason it was not was that this chip model is really not yet finished. Although it seemingly works, I have no experimental results on an overall realization to check the model results against, and to 'tweak' the model with. Consequently it is NOT RECOMMENDED that the circuit of Figure 20 be converted into a device, at least until such time that results are available. Consequently the controller chip model and the test circuit should be treated as a learning exercise until that time.
Bearing that in mind, it is interesting however to perform simulations with the circuit of Figure 21 to learn what we can from it.

Figure 22
Lm3430sm test graph 1

In this unexpanded circuit one can see the result of a step load change provided by controlled source I1 at the output. At t = 1mS, the load is lowered and at t = 2ms reapplied. This is shown in the green trace. Other interesting tests are to ramp up the input voltage source in a realistic manner, and see the effects of the delay in turn on of the controller chip, and to command the controller 'off' by command.
Some sub-harmonic oscillations seem to be present in the output. It is not known if this is 'real', which would not totally surprise me being a one-size-fits-all realization, or if this is a model error at this time. Actually, there is an error in the model, and it is caused by the improper use of the TED circuit. Instead of the TED output turning off the FF, it should be turned off at the end of the compensation ramp - see Figure 8. This could be part of the cause of what seem to be sub-harmonic oscillations.
Inasmuch as the model is tentative at this time, there seems little point in doing much more here. (If a reader is interested, and they provide me with a message with a 'real' email address, not a yahoo or other such email address, I will send them the circuit for them to examine as they wish.) The main utility of the model at this time however is as a learning tool to show some of the thinking in creating a controller chip model. This work was performed under contract; however, time and money did not enable me to finish the model.

Summary:
In this article a preliminary controller chip model was created, along with some other useful elements, which may be used to create other controller chip models. The model here is NOT complete and an error was noted which is present in the model. Nonetheless it illustrates some of the thinking and steps required in creating a controller chip model.

The World Of Technical Life

Monday 14 January 2013

SMPS Modeling

SMPS (Part 1) - Some basics

SMPS (Part 2) - Buck voltage mode averaged controller modeling

SMPS (Part 3) - Chris Basso Generic Switched Controller models

SMPS (Part 4) - Chris Basso Generic Switched Controller models

SMPS (Part 5) - LT3430 model

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